Method of fabricating gate

ABSTRACT

A method of fabricating a gate is described. A first dielectric layer having a first opening is formed on a substrate. A gate dielectric layer is formed in the opening. A lower portion of a floating gate is formed on the gate dielectric layer. A source/drain region is formed in the substrate beside the lower portion of the floating gate. A conductive layer is formed on the first dielectric layer to completely fill the first opening. The conductive layer is patterned to form a second opening in the conductive layer. The second opening is above the first opening and does not expose the first dielectric layer. The second opening has a tapered sidewall and a predetermined depth. A mask layer is formed to cover the conductive layer and fill the second opening. The mask layer outside the second opening is removed to expose the conductive layer. A portion of the mask layer is removed to leave a first etching mask layer in the second opening. An anisotropic etching process using the first etching mask layer as a mask is performed to etch the conductive layer. An upper portion of the floating gate is formed. The first dielectric layer is exposed. The first etching mask is removed. Thereafter, a dielectric layer between gates and a control gate is formed over the floating gate.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority benefit of Taiwanapplication serial no. 89119796, filed Sep. 26, 2000

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The invention relates to a fabrication method of forming a gateand a structure of a gate. More particularly, this invention relates toa method for increasing the effective surface area of the dielectriclayer between the gates (a dielectric layer between a floating gate anda control gate).

[0004] 2. Description of the Related Art

[0005] Stacked-gate non-volatile memory devices such as erasableprogrammable read only memory (EPROM), electrically erasableprogrammable read only memory (EEPROM) and flash memory, have attractedgreat attention and research due to excellent data storage propertieswithout applying additional electric field.

[0006] The current-voltage (I-V) characteristics of the stacked-gatenon-volatile memory devices can be derived from the I-V characteristicsand the coupling effect of the conventional metal-oxide semiconductor(MOS) device. Usually, the higher the capacitive coupling effect adevice has, the lower operation voltage is required.

[0007]FIG. 1 shows a structure of a conventional stacked-gatenon-volatile flash memory after forming and patterning conductive layers26 and 50. The conductive layers 26 and 50 construct a floating gate. Adielectric layer 24 is formed as the gate dielectric layer between thesubstrate and the floating gate. In FIG. 1B, a dielectric layer 52 isformed on the floating gate, and a control gate is formed on thedielectric layer 52. The control gate includes a conductive layer 54.Both FIGS. 1A and 1B have a gate 58 and a non-gate region 60. Theconductive layers 26 and 50 in the non-gate region 60 are removed whilepatterning the dielectric layer 52 and the conductive layer 54.

[0008]FIG. 2 shows a cross-sectional view of FIG. 1 taken along the lineII-II. In FIG. 2, a gate is formed on a substrate comprising asemiconductor substrate 20, a source region 22 and a drain region 23.The gate comprises the gate dielectric layer 24, the conductive layers26 and 50, the dielectric layer 52 and the conductive layer 54. Theconductive layer at least includes one layer. The gate dielectric layer24 is a dielectric layer between the gate and the substrate. Conductivelayers 26 and 50 together form a floating gate. The dielectric layer 52is a dielectric layer between gates. The conductive layer 54 is acontrol gate.

[0009] The conventional stacked-gate non-volatile flash memory comprisesfour junction capacitors. They are C_(FG) between the floating gate (theconductive layers 26 and 50) and the control gate (the conductive layer54), C_(B) between the floating gate and substrate 20, C_(S) between thefloating gate and the source region 22, and C_(D) between the floatinggate and the drain region 23.

[0010] The capacitive coupling ratio can be represented by:${{Capacitive}\quad {coupling}\quad {ratio}} = \frac{C_{FG}}{C_{FG} + C_{B} + C_{S} + C_{D}}$

[0011] According to the above equation, when the junction capacitorC_(FG) increases, the capacitive coupling ratio increases.

[0012] The method for increasing the junction capacitance C_(FG)includes increasing the effective surface of the dielectric layerbetween gates (the floating gate and the control gate), reducing thethickness of the dielectric layer between gates, and increasing thedielectric constant (k) of the dielectric layer between gates.

[0013] The dielectric layer between the floating gate and the controlgate requires a sufficient thickness to prevent the electrons within thefloating gate from flowing into the control gate during operation,resulting in device failure.

[0014] The increase of the dielectric constant of the dielectric layerbetween the floating gate and the control gate involves the replacementof fabrication equipment and the maturity of fabrication technique.Thus, it is not easy to increase the dielectric constant.

[0015] Therefore, increasing the effective surface area of thedielectric layer between the floating gate and the control gate becomesa trend for increasing the capacitive coupling ratio.

[0016] Referring to FIGS. 1A, 1B and 2, when the dielectric layer 52 andthe conductive layer 54 are patterned, the conductive layer 54, thedielectric layer 52, the conductive layers 50 and 26 in the non-gateregion are removed. Since the conductive layer 50 has a thickness, thevertical etching thickness of the dielectric layer 52 is greater thanthe lateral etching thickness of the dielectric layer 52. Thus, itcauses difficulty in etching. The dielectric layer residue of thedielectric layer 52 is even left.

[0017] The signal storage of the dynamic random access memory (DRAM) isperformed by selectively charging or discharging the capacitors on thesurface of a semiconductor substrate. The reading or writing operationis executed by injecting or ejecting charges from the storage capacitorconnected to a transfer field effective transistor and bit lines.

[0018] The capacitor is thus the heart of a dynamic random accessmemory. When the surface of the memory cell is reduced, the capacitanceis reduced. As a consequence, the read-out performance is degraded, theoccurrence of soft errors is increased, and the power consumption duringlow voltage operation is increased. Increasing the surface area of thedielectric layer between the bottom and top electrode becomes oneeffective method to resolve the above problems.

[0019]FIG. 3 is a schematic, cross-sectional view of a conventionalstacked gate. A device structure 82 is formed on the semiconductorsubstrate 80. A dielectric layer 84 is formed over the semiconductorsubstrate 80. An opening 86 is formed in the dielectric layer 84 toexpose the device structure 82. A bottom electrode connected to aconventional stacked transistor is formed to fill the opening 86 andcover a portion of the dielectric layer 84. Since the bottom electrode88 is a stacked type, the surface of the bottom electrode 88 is limitedby its shape The bottom electrode 88 for the conventional stacked-typetransistor is not great Cylinder capacitors have increased surfaceareas. However, many photomasks are required in the fabrication process.The fabrication is complex and time-consuming.

SUMMARY OF THE INVENTION

[0020] The invention provides a fabrication method and structure of agate. The present invention increases the effective surface of thedielectric layer between gates (the floating gate and the control gate).In addition, the vertical etching thickness of the dielectric layerbetween gates is reduced.

[0021] In the present invention, a first dielectric layer having a firstopening is formed on a substrate. A gate dielectric layer is formed inthe opening. A lower portion of a floating gate is formed on the gatedielectric layer. A source/drain region is formed in the substratebeside the lower portion of the floating gate. A conductive layer isformed on the first dielectric layer to completely fill the firstopening. The conductive layer is patterned to form a second opening inthe conductive layer. The second opening is above the first opening anddoes not expose -he first dielectric layer. The second opening has atapered sidewall and a predetermined depth. A mask layer is formed tocover the conductive layer and fill the second opening. The mask layeroutside the second opening is removed to expose the conductive layer. Aportion of the mask layer is removed to leave a first etching mask layerin the second opening. An anisotropic etching process using the firstetching mask layer as a mask is performed to etch the conductive layer.An upper portion of the floating gate is formed. The first dielectriclayer is exposed. The first etching mask is removed. Thereafter, adielectric layer between gates and a control gate is formed over thefloating gate.

[0022] In the above-described method, the conductive layer has thesecond opening. The second opening has a tapered sidewall. The secondopening is filled with the first etching mask layer. In addition, thefirst etching mask does not cover the conductive layer outside thesecond opening. Thus, the first etching mask is used as a mask whileperforming anisotropic etching to form the upper portion of the floatinggate. Thus, no additional photomask is required. Thus, the inventionreduces the use of one photomask.

[0023] The upper portion of the floating gate has the second opening. Incomparison with the conventional stacked floating gate, the upperportion of the floating gate has an increased surface area. Moreover,the upper portion of the floating gate is formed by anisotropic etchingthe conductive layer using the first etching mask as a mask. Inaddition, the second opening in the floating gate has the taperedsidewall. Thus, the upper portion of the floating gate has tapered outerand inner sidewalls.

[0024] The above-described method further includes the following steps.A second dielectric layer is formed over the substrate. The seconddielectric layer is conformal to the upper portion of the floating gate.At least one second conductive layer is formed to cover the seconddielectric layer. A second etching mask layer having a pattern is formedover the second conductive layer. The pattern exposes a portion of theupper portion of the floating gate. A second anisotropic c etchingprocess is performed using the second etching mask as a mask. The secondconductive layer, the second dielectric layer, the upper portion of thefloating gate, a lower portion of the floating gate are etched insequence to expose a portion of the first dielectric layer, and the gatedielectric layer underlying the lower portion of the floating gate.After the second dielectric layer is etched, a dielectric layer betweengates is formed on the upper portion of the floating gate. After thesecond conductive layer is etched, a control gate is formed on thedielectric layer between the gates. The second evening mask is removed.

[0025] In the above-described method, the dielectric layer between gatesis conformal to the upper portion of the floating gate. Therefore, thedielectric layer between gates has an increased surface area. Theperformance of the gate is enhanced. The capacitance between thefloating ate and the control gate is increased.

[0026] In addition, the dielectric layer between gate also has a taperedsurface on the tapered inner and outer sidewalls of the upper portion ofthe floating gate. When the anisotropic etching is performed to etch thedielectric layer between gates, the vertical etching thickness of thedielectric layer between gates is reduced. Thus, the dielectric layerbetween gates in the non-gate region is easily removed.

[0027] In the present invention, the angle between the sidewall of thesecond opening in the floating gate and the horizontal is about 60degrees to about 90 degrees. The material of the mask layer is oneselected form. The group consisting of photoresist material, spin-onglass, oxide, silicon nitride doped oxide, doped silicon nitride,borosilicate glass (BSG), borophosphosilicate giass (BPSG), boro-oxide,phospho-oxide, borophospho-oxide, or organic silicide containing,silicon and oxide. The mask layer outside the second opening can beremoved by etching or chemical mechanical polishing. The predetermineddepth of the second opening is about 30% of a thickness of theconductive layer above the first dielectric layer For example, the upperportion of the floating gate can cover a portion of the first dielectriclayer surrounding the first opening.

[0028] An invention further provide a gate structure formed on asubstrate. The substrate comprises a source/drain region. A dielectriclayer is formed over a substrate. A first opening is formed in the gatedielectric layer A gate dielectric is formed on the substrate exposed bythe first opening. A lower portion of a floating gate is formed on thegate dielectric layer. The first opening is filled with an upper portionof the floating gate. The upper portion of the floating gate and thelower portion of the floating gate are electrically connected. The upperportion or the floating gate has a tapered outer sidewall. A secondopening having a tapered sidewall is formed in the upper portion of thefloating gate. The second opening having a self-determined depth islocated above the first opening. A dielectric layer between gates isformed over the floating gate. The dielectric layer between gates isconformal to -he upper portion of the floating gate. A control gate isformed over the dielectric layer between gates.

[0029] In the above-described gate structure, the upper portion of thefloating gate has a tapered outer sidewall. The second opening in theupper portion of the floating gate has a tapered sidewall. Thus, theupper portion of he floating gate has an increased surface and hastapered inner and outer sidewalls. In addition, the dielectric layerbetween gates is conformal to the upper portion of the floating gate.Thus, the dielectric layer between gates has an increased surface. Thedielectric layer between gates in the non-gate region can be easilyremoved. As the surface area of the dielectric layer between gates isincreased, the performance of the gate is enhanced. The capacitancebetween the floating gate and the control gate is increased.

[0030] According to the above-described method and structure, thepresent invention can also be used for forming a DRAM capacitor base onthe same mechanism, in the DRAM capacitor, the gate dielectric layer isa capacitor dielectric layer. The floating gate is the bottom electrodeThe control is an upper electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031]FIG. 1A illustrates a layout of a conventional stacked-gatenon-volatile flash memory after forming the floating gate;

[0032]FIG. 1B illustrates the layout of the gate of the stacked-gatenon-volatile flash memory as shown in FIG. 1A;

[0033]FIG. 2 illustrates a cross-sectional view of FIGS. 1A and 1B takenalong the cutting line II-II′;

[0034]FIG. 3 illustrate a conventional stacked capacitor;

[0035]FIG. 4A illustrates a layout of the stacked-gate memory afterforming the floating gate according to one preferred embodiment of thepresent invention;

[0036]FIG. 4B illustrates the layout of the gate of the stacked-gatenon-volatile flash memory as shown in FIG. 4A;

[0037]FIG. 5A through FIG. 5H are cross-sectional views of FIGS. 4A ad4B taken along the cutting line IV-IV; and

[0038]FIG. 6A through FIG. 6G shows the application of the methodprovided by the invention to a dynamic random access memoir

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

[0040] The present invention provides a gate of the stacked-gatenon-volatile flash memory and its fabrication method. The methodincludes forming an upper portion of the floating gate. The upperportion of the floating gate has a tapered sidewall. The upper portionof the floating gate has an opening with a tapered sidewall. Thus, theupper portion of the floating gate has both tapered inner and outersidewalls.

[0041] First Embodiment

[0042]FIG. 4A illustrates a layout of the stacked-gate memory afterconductive layers 108 and 116 are formed. The conductive layers 108 and116 together form a floating gate. A gate dielectric layer 106 is formedbetween the floating gate and a substrate. The gate region 158 and thenon-gate region 160 have the same structure thereon.

[0043]FIG. 4B illustrates the layout of the gate of the stacked-gatenon-volatile flash memory as shown in FIG. 4A. A dielectric layer 122 isformed between the floating gate and a control gate. That is thedielectric layer 122 is a dielectric layer between gates. A conductivelayer 124 is formed as the control gate. The conductive layer 124 atleast has one layer. A gate region 158 includes a gate dielectric layer106, the conductive layers 108 and 116, a dielectric layer 233, and theconductive layer 124. The conductive layers 108 and 116 b in a non-gateregion 160 are removed while patterning the dielectric layer 122 and theconductive layer 124. The conductive layer 124 between the gate regions158 constitutes bit lines (not shown) for connecting gates.

[0044]FIG. 5A through FIG. 5H are cross-sectional views of FIGS. 4A ad4B taken along the cutting line IV-IV′.

[0045] Referring to FIG. 5A, a semiconductor substrate 100 is provided.A source region 102, a drain region 104, the gate dielectric layer 106,the dielectric layer 112 are formed. The dielectric layer 112 is formedover the semiconductor substrate 100. An opening 114 is formed in thedielectric layer 112. The conducive layer 108 having a top surface lowerthan that of the dielectric layer 112 is formed in the opening 114.

[0046] Referring to FIG. 5B, the conductive layer 116 is formed over thedielectric layer 112 to fill the opening 114. The material of theconductive layer 116 includes polysilicon.

[0047] Referring to FIG. 4A and 5C, an etching mask layer for formingthe conductive layer 116 b as shown in FIG. 4A is formed over theconductive layer 116. As shown in FIG. 5C, the etching mask layer isused to pattern the conductive layer 116. A conductive layer 116 ahaving an opening 118 is formed. The opening 118 is above the opening114 and does not expose the dielectric layer 112. The opening 118 has atapered sidewall. An angle 119 between the tapered sidewall of theopening 118 the horizontal is from about 60 degrees to about 90 degrees.The opening 118 has a predetermined depth. The predetermined depth ofthe opening 118 is at least about 30% of the thickness of the conductivelayer 116 a above the dielectric layer 112.

[0048] Referring to FIG. 5D, a mask layer 120 is formed to cover theconductive layer 116 to fill the opening 118. The material of the masklayer 120 includes photoresist material, spin-on glass, oxide, siliconnitride, doped oxide, doped silicon nitride, borosilicate glass (BSG),borophosphosilicate glass (BPSG), boro-oxide, phospho-oxide,borophospho-oxide, or organic silicide containing silicon or oxide. Ifthe mask layer 120 is spin-on glass, after the mask layer 120 has beencoated, the mask layer 120 needs to be solidified.

[0049] Referring to FIG. 5E, a portion of the mask layer 120 is removedby, for example, etching or chemical-mechanical polishing. In the casethat the mask layer 120 is oxide, silicon nitride, doped oxide, dopedsilicon nitride, borosilicate glass (BSG), borophosphosilicate glass(BPSG), boro-oxide, phospho-oxide, borophospho-oxide, or organicsilicide containing silicon and oxide, the mask layer 120 can be removedby etching or chemical-mechanical polishing. In the case that the masklayer 120 is photoresist or spin-on glass, the mask layer 120 can beremoved by etching. After a portion of the mask layer 120 is removed, amask layer 120 a filling the opening 118 is left in the conductive layer116 a. The conductive layer 116 a outside the opening 118 is exposed.

[0050] Referring to FIG. 5F, an etching, such as an anisotropic etching,using the mask layer 120 a as a mask is performed to etch the conductivelayer 116 a. A conductive layer 116 b is formed to expose a portion ofthe dielectric layer 112. The conductive layer 116 b has an outertapered sidewall. The angle 121 between the outer tapered sidewall andthe horizontal is about 60 degrees to about 90 degrees. The conductivelayer 116 b covers a portion of the dielectric layer 112 surrounding theopening 114.

[0051] Referring to FIG. 5G, the mask layer 120 a is removed to completethe upper portion of the floating gate of the stacked-gate non-volatileflash memory. That is, the conductive layer 116 b is formed. Theconductive layer 108 and the conductive layer 116 b together form afloating gate. The conductive layer 108 and the conductive layer 116 bof the FIG. 4A show the layout of the floating gate.

[0052] The conductive layer 116 a has the opening 115. The opening 118has a tapered sidewall. The opening 118 is filled with the mask layer120. Thus, the mask layer 120 a can serve as a mask when the conductivelayer 116 a is etched to form the conductive layer 116 b. Thus, noadditional photomask is needed to pattern the conductive layer 116 a.The number of photomasks required is decreased.

[0053] In the conventional stacked-gate non-volatile flash memory, thesurface area of conductive layer 50 is limited by its shape and thus thesurface area is not great. In the present invention, since theconductive layer 116 b has the opening 118, as shown in FIG. 5G, thesurface area of the conductive layer 116 b is increased.

[0054] The opening 118 of the conductive layer 116 a has a taperedsidewall. In addition, the conductive layer 116 b is formed byanisotropic etching the conductive layer 116 a. Thus, the conductivelayer 116 b has a tapered outer sidewall. Therefore, the conductivelayer 116 b has tapered outer and inner sidewalls.

[0055] Thereafter, a dielectric layer between gates conformal to theconductive layer 116 b is formed over the conductive layer 116 b and thedielectric layer 112. A control gate layer is formed over the dielectriclayer between the gates. As shown in FIGS. 4A and 4B and 5H, an etchingmask for forming the conductive layer 124 of FIG. 4B is formed over thecontrol gate layer. Using the etching mask, in the non-gate region 160,the control gate layer, the dielectric layer between gates, theconductive layer 116 b, and the conductive layer 118 are etched insequence to expose the gate dielectric layer 106. At the same time, thecontrol gate layer and the dielectric layer between gates in thenon-gate region and exposed by the mask layer are removed to expose thedielectric layer 112. The etching mask is removed to form the conductivelayer 124, the dielectric layer 122. A gate in the gate region 158 andword lines, which connect the gate regions, are formed.

[0056] The dielectric layer 122 in the gate region 158 and theconductive layer 116 b have the same shape. Thus, the surface area isincreased. The dielectric layer 122 is the dielectric layer betweengates. The conductive layer 124 is a control gate. Thus, the capacitancebetween the floating gate and the control gate is increased.

[0057] Since the dielectric layer between gates is conformal to theconductive layer 116 b, the shape of the dielectric layer between gatesin the non-gate region 160 has the same shape as the conductive layer116 b. The conductive layer 116 b has a tapered inner and outersidewall, the dielectric layer between gates in the non-gate region 160also has a tapered surface. The vertical etching thickness of thedielectric layer between gates in the non-gate region 160 thus isreduced. As a result, the dielectric layer between the gates in thenon-gate region 160 is effectively removed.

[0058] The material of the dielectric layer 122 includes siliconnitride, silicon oxide, oxide/nitride/oxide (ONO), lead zirconiumtitanate, bismuth strontium titanate or tantalum oxide. The conductivelayer 124 includes at least a layer of conductive material. The materialof the conductive layer 124 includes polysilicon or tungsten silicide.

[0059] Second Embodiment

[0060]FIGS. 6A through 6G illustrate the fabrication process of forminga electrode according to the present invention. Referring to FIG. 6A, asemiconductor substrate 200 is provided. An isolated region 202 isformed in the semiconductor substrate 200 to define the active regionsof devices. A DRAM transistor is formed on the semiconductor substrate200. The transistor includes a source/drain region 204, a gatedielectric layer 206, a gate 208, and a spacer 210. A dielectric layer212 is formed over the semiconductor substrate 200. An opening 214 isformed in the dielectric layer 212 to expose the source/drain region 204of the transistor.

[0061] Referring to FIG. 6B, a conductive layer 216 is formed over thedielectric layer 212 to fill the opening 214. The material of theconductive layer 216 includes polysilicon.

[0062] Referring to FIG. 6C, the conductive layer 216 is patterned toform a conductive layer 216 a. The conductive layer 216 a has an opening218. The opening 218 is above the opening 214. The opening 218 does notexpose the dielectric layer 212 and has a tapered sidewall. An angle 219between the tapered sidewall and the horizontal is about 60 degrees toabout 90 degrees. The opening 218 has a predetermined depth. Thepredetermined depth of the opening 218 is at least about 30% of thethickness of the conductive layer 216 a above the dielectric layer 212.

[0063] Referring to FIG. 6D, a mask layer 220 is formed to cover theconductive layer 216 a and fill the opening 218. The material of themask layer 230 includes photoresist, spin-on glass, oxide, siliconnitride, doped oxide, doped silicon nitride, borosilicate glass (BSG),borophosphosilicate glass (BPSG), boro-oxide, phospho-oxide,borophospho-oxide, or organic silicide containing silicon and oxide. Inthe case that the mask layer 220 is a spin-on glass layer, after themask layer 220 has been coated, the mask layer 220 needs to besolidified.

[0064] Referring to FIG. 6E, a portion of the mask layer 220 is removedby, for example, etching or chemical-mechanical polishing. In the casethat the mask layer 220 is oxide, silicon nitride, doped oxide, dopedsilicon nitride, borosilicate glass (BSG), borophosphosilicate glass(BPSG), boro-oxide, phospho-oxide, borophospho-oxide, or organicsilicide containing silicon and oxide, the mask layer 220 can be removedby etching or chemical-mechanical polishing. In the case that the masklayer 220 that the mask layer 220 is photoresist or spin-on glass, themask layer 220 can be etching. After a portion of the mask layer 220 isremoved, a mask layer 220 a is left to fill the opening 218 in theconductive layer 216 a. The conductive layer 216 a outside the opening118 is exposed.

[0065] Referring to FIG. 6F, an etching, such as an anisotropic etching,using the mask layer 220 a as a mask is performed. A conductive layer216 a is etched to form a conductive layer 216 b. The conductive layer216 b exposes a portion of the dielectric layer 212.

[0066] Referring to FIG. 6G, the mask layer 220 a is removed to completethe upper portion of the floating gate of the stacked-gate non-volatileflash memory. That is, the conductive layer 216 b is formed. Theconductive layer 216 b has a tapered outer sidewall. An angle 217between the tapered outer sidewall and the horizontal is about 60degrees to about 90 degrees. The conductive layer 216 b covers a portionof the dielectric layer 212 surrounding the opening 214.

[0067] The opening 218 has a tapered sidewall. The mask layer 220 fillsthe opening 218. Thus, the mask layer 220 a can serve as a mask when theconductive layer 216 a is etched to form the conductive layer 216 b.Thus, no additional photomask is needed when the conductive layer 116 ais patterned. The number of required photomasks is decreased.

[0068] The shape of the conventional stacked capacitor limits thesurface area of storing charges. In the foregoing embodiment, becausethe conductive layer 216 b has the opening 218. The conductive layer 216b has a cylindrical or ring shape. The capacitance of the capacitor isincreased.

[0069] In summary, the invention provides at least the followingadvantages:

[0070] (1) The opening in the upper portion of the floating gate isfilled with the mask layer. The mask layer is used as a mask when anetching step is performed to form the upper portion of the floatinggate. No additional photomask is required. Thus, the present inventionreduces the use of one photomask.

[0071] (2) The upper portion of the floating gate has the opening. Thus,the upper portion of the floating gate formed by the present inventionhas an increased surface and a tapered inner and outer sidewalls.

[0072] (3) After a gate on the upper portion of the floating gate isformed, the surface area of the dielectric layer between the gate isincreased. The vertical etching thickness of the dielectric layerbetween gates in the non-gate region is reduced. Thus, the effectivesurface area of the dielectric layer between the gates is increased.

[0073] (4) The performance of the gates is enhanced. The capacitancebetween the floating gate and the control gate is increased.

[0074] (5) According to the same theory, the above-described opening canalso used for forming a DRAM capacitor. The surface area of thecapacitor dielectric layer is increased, and consequently, thecapacitance of the capacitor is increased.

[0075] It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure and the methodof the present invention without departing from the scope or spirit ofthe invention. In view of the foregoing, it is intended that the presentinvention cover modifications and variations of this invention providedthey fall within the scope of the following claims and theirequivalents.

What is claimed is:
 1. A method of fabricating a gate over a substrate,which comprises a first dielectric layer having a first opening formedthereon, a gate dielectric layer formed in the opening, a lower portionof a floating gate formed on the gate dielectric layer, a source/drainregion formed in the substrate beside the lower portion of the floatinggate, comprising: forming a conductive layer on the first dielectriclayer to completely fill the first opening; patterning the conductivelayer to form a second opening in the conductive layer, wherein thesecond opening is above the first opening and does not expose the firstdielectric layer, and the second opening has a tapered sidewall and apredetermined depth; forming a mask layer to cover the conductive layerand fill the second opening; removing the mask layer outside the secondopening to expose the conductive layer, wherein a portion of the masklayer is removed to leave a first etching mask layer in the secondopening; performing an anisotropic etching process using the firstetching mask layer as a mask to etch the conductive layer, wherein anupper portion of the floating gate is formed, and the first dielectriclayer is exposed; and removing the first etching mask.
 2. The method ofclaim 1, wherein mask layer is one selected from the group consisting ofphotoresist material, spin-on glass, oxide, silicon nitride, dopedoxide, doped silicon nitride, borosilicate glass (BSG),borophosphosilicate glass (BPSG), boro-oxide, phospho-oxide,borophospho-oxide, or organic silicide containing silicon and oxide. 3.The method of claim 1, wherein the mask layer outside the second openingis removed by etching or chemical mechanical polishing.
 4. The method ofclaim 1, wherein an angle between the tapered sidewall of the secondopening and a horizontal is about 60 degrees to about 90 degrees.
 5. Themethod of claim 1, wherein the predetermined depth of the second openingis about 30% of a thickness of the conductive layer above the firstdielectric layer.
 6. The method of claim 1, wherein the upper portion ofthe floating gate covers a portion of the first dielectric layersurrounding the first opening.
 7. The method of claim 1, wherein theupper portion of the floating gate includes polysilicon.
 8. The methodof claim 1, further comprising: forming a second dielectric layer overthe substrate, wherein the second dielectric layer is conformal to theupper portion of the floating gate; forming at least one secondconductive layer to cover the second dielectric layer; forming a secondetching mask layer having a pattern over the second conductive layer,wherein the pattern exposes a portion of the upper portion of thefloating gate; performing a second anisotropic etching process using thesecond etching mask as a mask to etch the second conductive layer, thesecond dielectric layer, the upper portion of the floating gate, a lowerportion of the floating gate in sequence to expose a portion of thefirst dielectric layer, and the gate dielectric layer underlying thelower portion of the floating gate, wherein after the second dielectriclayer is etched, a dielectric layer between gates is formed on the upperportion of the floating gate, and after the second conductive layer isetched, a control gate is formed on the dielectric layer between thegates; and removing the second etching mask.
 9. The method of claim 8,wherein a material of the dielectric layer between gates is one selectedfrom the group consisting of silicon nitride, silicon oxide,oxide/nitride/oxide (ONO), lead zirconium titanate, bismuth strontiumtitanate, or tantalum oxide.
 10. The method of claim 8, wherein amaterial of the control gate is polysilicon or tungsten silicide.
 11. Amethod of forming a bottom electrode of a capacitor, comprising:providing a substrate, wherein the substrate includes a device; forminga dielectric layer having a first opening over the substrate, whereinthe first opening expose the device; forming a conductive layer over thedielectric layer to fill the first opening; patterning the conductivelayer to form a second opening in the conductive layer, wherein thesecond opening has a predetermined depth and a tapered sidewall, thesecond opening and is above the first opening and does not expose thedielectric layer; forming a first mask layer to cover the conductivelayer to fill the second opening; removing a portion of the first masklayer outside the second opening to expose the conductive layer, whereina second mask layer is formed in the second opening; performing ananisotropic etching using the second mask layer as a mask to etch theconductive layer so as to form a bottom electrode, wherein thedielectric layer is exposed; and removing the mask layer.
 12. The methodof claim 11, wherein mask layer is one selected from the groupconsisting of photoresist material, spin-on glass, oxide, siliconnitride, doped oxide, doped silicon nitride, borosilicate glass (BSG),borophosphosilicate glass (BPSG), boro-oxide, phospho-oxide,borophospho-oxide, or organic silicide containing silicon and oxide. 13.The method of claim 11, wherein the mask layer outside the secondopening is removed by etching or chemical mechanical polishing.
 14. Themethod of claim 11, wherein an angle between the tapered sidewall of thesecond opening and a horizontal is about 60 degrees to about 90 degrees.15. The method of claim 11, wherein the bottom electrode covers aportion of the dielectric layer around the first opening.
 16. The methodof claim 11, wherein the predetermined depth of the second opening is30% of a thickness of the conductive layer above the dielectric layer.17. The method of claim 1, wherein the conductive layer includespolysilicon.
 18. A gate structure formed on a substrate, wherein thesubstrate comprises a source/drain region, comprising: a dielectriclayer formed over a substrate; a first opening formed in the gatedielectric layer; a gate dielectric formed on the substrate exposed bythe first opening; a lower portion of a floating gate formed on the gatedielectric layer; and an upper portion of the floating gate at leastfilling in the first opening, wherein the upper portion of the floatinggate and the lower portion of the floating gate are electricallyconnected, the upper portion of the floating gate has a tapered outersidewall, and a second opening having a tapered sidewall formed in theupper portion of the floating gate, wherein the second opening having apredetermined depth is located above the first opening.
 19. Thestructure of claim 18, wherein an angle of a sidewall of the secondopening is about 60 degrees to about 90 degrees.
 20. The structure ofclaim 18, wherein an angle of a sidewall of the second opening is about60 degrees to about 90 degrees.
 21. The structure of claim 18 whereinthe upper portion of the floating gate covers a portion of thedielectric layer surrounding the second opening.
 22. The structure ofclaim 18, wherein the predetermined depth of the second opening is 30%of a thickness of the conductive layer above the dielectric layer. 23.The structure of claim 18, wherein the upper portion of the floatinggate is polysilicon or tungsten silicide.
 24. The method of claim 18,further comprising: a dielectric layer between gates formed on the upperportion of the floating gate; and a control gate is formed on thedielectric layer between the gates.
 25. The structure of claim 24, amaterial of the dielectric layer between the gates is selected from thegroup consisting of silicon nitride, silicon oxide, oxide/nitride/oxide(ONO), lead zirconium titanate, bismuth strontium titanate, or tantalumoxide.
 26. The structure of claim 24, wherein a material of the controlgate is polysilicon or tungsten silicide.
 27. A bottom electrode of acapacitor formed on a substrate, wherein the substrate has a device,comprising: a dielectric layer formed over the substrate, wherein thedielectric layer has a first opening exposing the device in thesubstrate; and a bottom electrode at least filling in the first openingin the dielectric layer, wherein the bottom electrode electricallyconnects to the device, a second opening is formed in the dielectriclayer, and the second opening has a tapered sidewall and a predetermineddepth.
 28. The structure of claim 27, wherein the bottom electrode has atapered sidewall.
 29. The structure of claim 28, wherein an anglebetween the tapered sidewall and a horizontal is about 60 degrees toabout 90 degrees.
 30. The structure of claim 27, wherein a angle betweena tapered sidewall of the second opening and a horizontal is about 60degrees to about 90 degrees.
 31. The structure of claim 27, wherein thebottom electrode covers a portion of the dielectric layer surroundingthe first opening.
 32. The structure of claim 27, wherein thepredetermined depth of the second opening is at least about 30% of athickness of the bottom electrode above the dielectric layer.
 33. Thestructure of claim 27, wherein a material of the bottom electrodecomprises polysilicon.